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| EM7A8620 Voice over IP Product Specification DOC. VERSION 1.0 ELAN MICROELECTRONICS CORP. January 2006 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright (c) 2005 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of in this specification are subject to change without notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible to any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising out of the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: No. 12, Innovation Road 1 Science-based Industrial Park Hsinchu, Taiwan, 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: USA: Elan Information Technology Group 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220 Europe: Shanghai: Elan Microelectronics Shanghai Corporation, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600 Elan Microelectronics Corp. Elan Microelectronics (Europe) Shenzhen, Ltd. Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 Contents 1. INTRODUCTION 1.1 1.2 1.3 1.4 1.5 FEATURE APPLICATION SIGNAL DESCRIPTIONS SYSTEM BLOCK DIAGRAM PIN ASSIGNMENT 1 1 2 3 6 7 8 8 8 8 8 9 9 9 10 10 10 10 11 11 11 11 12 12 13 13 13 13 13 14 2. FUNCTION DESCRIPTIONS 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 CPU SDRAM CONTROLLER STATIC MEMORY CONTROLLER 10/100 ETHERNET DIRECT MEMORY ACCESS I2C UART I2S/SPI CONTROLLER PCM CONTROLLER LCD DOT MATRIX CONTROLLER TIMER WATCH DOG TIMER (WDT) INTERRUPT CONTROLLER GENERAL PURPOSE INPUT / OUTPUT REAL TIME CLOCK POWER MANAGEMENT AUDIO CODEC 3. DC CHARACTERISTICS 3.1 3.2 3.3 3.4 3.5 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS I/O PAD CAPACITANCE DC CHARACTERISTICS FOR 3.3V OPERATION DC CHARACTERISTICS FOR 1.8V OPERATION Product Specification (V1.0) 3.08.2006 *6 Contents Specification Revision History Version Revision Description 1.0 Preliminary version Date 2006/03/08 iv * Product Specification (V1.0) 1.2006 EM7A8620 Voice Over IP 1. Introduction The EM7A8620 is a high integrated and high-performance ASIC. It integrated with the high performance 32-bit RISC CPU, 16-bit high quality audio Codec and two 802.3 Ethernet PHYs. The ASIC also built in a number of on-chip communications peripherals, like I2S/ I2C/PCM Bus/SPI/UART...etc. This is ideal chip to be integrated into Voice over IP or Adapter phone solution. 1.1 Feature -32-bit RISC Embedded processor 32-bit RISC with 16KB I-Cache/16KB D-Cache Memory Management Unit AMBA-AHB bus AMBA-APB bus SDRAM Controller Static Memory Controller Two 10/100 Ethernet MAC controllers and PHYs Direct Memory Access Controller Unified memory bus interface I2C Controller 16550-compatible UART Three I2S/SPI Controller Embedded audio CODEC PCM Controller Two 6-ch Internal Timer Watch Dog Timer 64-ch Interrupt Controller LCD (dot matrix) controller interface 32-bit General Purpose I/O (GPIO) -System Bus -Components on AHB bus -Components on APB bus -Power & Clock Management Embedded PLL for programmable clocks Frequency: As high as 196 MHz for CPU at commercial conditions -Operation Voltage Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) *1 EM7A8620 Voice Over IP 1.8V for Core 3.3V for Input/Output -Package Type: 208-QFP 1.2 APPLICATION -DECT Application -VOIP Phone 2* Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) EM7A8620 Voice Over IP -VOIP Adapter 1.3 Signal Descriptions Table 1 Signal Descriptions for the VoIP ASIC Processor Pin name Dir Description SDRAM/SRAM Address/Data Bus MEMADDR[25] / LCD_E MEMADDR[24] / LCD_RS MEMADDR[23] / LCD_RWn MEMADDR[22:15] / LCD_DB[7:0] MEMADDR[14:0] MEMDATA[31:0] SDRAM_CKE SDRAM_RASn SDRAM_CASn SDRAM_CSn EBI_WEn EBI_BEn[3:0] SDCLK SMC_CS0n SMC_OEn O O O IO O IO O O O O O O O O O SRAM address bit-25 / LCD controller, register select LCD controller, read/write start SRAM address bit-24 / LCD controller, read/write command SRAM address bit-23 to bit-16 / LCD controller, data bus bit-7 to bit-0 SDRAM/SRAM Memory address bus. SDRAM/SRAM Memory data bus. SDRAM clock enable. SDRAM row address strobe. Active LOW. SDRAM column address strobe. Active LOW. SDRAM chip select. Active LOW. SDRAM/SRAM write enable. Active LOW. SDRAM DQM for data bytes 3 through 0. SDRAM clocks. SRAM chip select SRAM output enable ICE ICK / GPIO[29] IMS / GPIO[28] IO IO ICE clock input / GPIO bit-29 ICE mode select / GPIO bit-28 *3 Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) EM7A8620 Voice Over IP ID / GPIO [27] EXTGOICE / GPIO[26] IO IO ICE data / GPIO bit-27 ICE enable / GPIO bit-26 GPIO GPIO[25:0] IO General purpose I/O PCM PCM_TXD PCM_RXD PCM_FSYN PCM_BCLK O I IO IO PCM transmit data PCM receive data PCM frame sync. PCM bit clock SPI/I2S SSP[1:3]_SCLK SSP[1:3]_FS SSP[1:3]_RXD SSP[1:3]_TXD SSP_CLKOUT IO IO I O O SPI bit clock SPI frame sync SPI RX SPI TX I2S main clock I2C I2C clock. I2C data. UART SCL SDA IO IO SIN / GPIO[31] SOUT / GPIO[30] I O Full function UART receive. Full function UART transmit. Global Reset RSTn I Hardware reset. Oscillator Pad OSCHIN OSCHIO I IO 12 MHz crystal input. 12 MHz crystal output. Ethernet PHY 1 PHY1_RXIP PHY1_RXIN PHY1_TXOP PHY1_TXON PHY1_XTLP PHY1_XTLN PHY1_VCCA0 PHY1_GNDA0 PHY1_VCCD2 PHY1_GNDD2 PHY1_VCCA3 PHY1_GNDA3 PHY1_RSET_BG PHY1_LINKLED PHY1_SPDLED 4* IO IO IO IO I I I I I O IO I O O O Differential signal pair RX Differential signal pair RX Differential signal pair TX Differential signal pair TX Crystal input Crystal input VCCA set 0 GNDA set 0 VCCD set 2 GNDD set 2 VCCA set 3 GNDA set 3 12.3 K to GND LED signal indicates the link status LED signal indicates the 10/100 speed Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) EM7A8620 Voice Over IP Ethernet PHY 2 PHY2_RXIP PHY2_RXIN PHY2_TXOP PHY2_TXON PHY2_XTLP PHY2_XTLN PHY2_VCCA0 PHY2_GNDA0 PHY2_VCCD2 PHY2_GNDD2 PHY2_VCCA3 PHY2_GNDA3 PHY2_RSET_BG PHY2_LINKLED PHY2_SPDLED IO IO IO IO I I I I I O IO I O O O Differential signal pair RX Differential signal pair RX Differential signal pair TX Differential signal pair TX Crystal input Crystal input VCCA set 0 GNDA set 0 VCCD set 2 GNDD set 2 VCCA set 3 GNDA set 3 12.3 K to GND LED signal indicates the link status LED signal indicates the 10/100 speed Audio CODEC Headphone amplifier analog ground pad Analog head phone, right channel Analog head phone, left channel Headphone amplifier analog power pad, 3.3V Analog microphone input Analog line input, left channel Analog line input, right channel Analog power pad, 3.3V Analog common-mode voltage Analog ground pad Analog line out, right channel Analog line out, left channel DLL HCLK I DLL feedback clock Test TEST I 1: test mode, 0: normal mode DLL / PLL / OSC Power VCC18A_PLL[1:2] GNDA_PLL[1:2] VCC18A_DLL GNDA_DLL VCC18IO_OSC GNDIO_OSC I I I I I I PLL analog power (1.8V). PLL analog ground DLL analog power (1.8V). DLL analog ground OSCH power (1.8V). OSCH ground CODEC_GNDA_HP CODEC_RHPOUT CODEC_LHPOUT CODEC_VCCA_HP CODEC_MICIN CODEC_LLINEIN CODEC_RLINEIN CODEC_VCCA CODEC_VCM CODEC_GNDA CODEC_ROUT CODEC_LOUT I O O I I I I I O I O O Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) *5 EM7A8620 Voice Over IP 1.4 System Block Diagram 16-bit CODEC PHY PHY External Bus Interface (EBI) 32-bit RISC 200Mhz 10/100 Ethernet MAC 10/100 Ethernet MAC SDRAM Controller SRAM/ROM/ Flash Controller AHB DMA Controller AHB Controller AHB to APB Bridge APB PMU Interrupt Controller Timer, WDT GPIO,I2C, UART Keypad controller IIS, PCM Codec, SLIC, T1/E1 Interface Figure 1 Block Diagram of EM7A8620 6* Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) EM7A8620 Voice Over IP 1.5 Pin Assignment Figure 2 Block Diagram of EM7A8620 Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) *7 EM7A8620 Voice Over IP 2. Function Descriptions 2.1 CPU The CPU is a general-purpose 32-bit embedded RISC processor. It's a Harvard architecture design with six pipeline stages. It includes separate instruction / data caches, separate instruction / data scratchpads, a write buffer, a branch target buffer, a protection unit, and an ICE interface. 2.2 SDRAM Controller The SDRAM memory controller supports one 8-, 16- or 32-bit wide bank. The SDRAM controller performs auto-refreshing during normal operation, and supports SDRAM self-refreshing during Sleep. The SDRAMC shares the address / data bus with Static Memory Controller. The SDRAMC features include: Wide address range up to 256 M bytes Support various SDRAM types Support a programmable auto-refresh and self-refresh 2.3 Static Memory Controller The Static Memory Controller supports Flash memory, SRAM and ROM. Each chip select can be individually programmed to an 8-, 16- or 32-bit wide data bus. The features include: Support ROM, FLASH, burst-ROM, asynchronous SRAM Wide address range up to 64M bytes 2.4 10/100 Ethernet The Ethernet MAC 10/100 is a high quality 10/100 Ethernet controller with DMA functions. It includes AHB interface, DMA channel, MAC, and PHY. The Ethernet features include: 10Mbps/100Mbps operation Half and Full duplex modes Support flow control for full duplex and backpressure for half duplex Fully compliant with IEEE 802.3u, FDDI-TP-PMD and IEEE 802.3 Support Auto Negotiation detection and Auto Crossover detection Network status LEDs 8* Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) EM7A8620 Voice Over IP 2.5 Direct Memory Access The DMA provides up to 4 channels for memory-to-memory, memory-to-peripheral, peripheral-to-peripheral, and peripheral-to-memory transfer with the shared buffer. The features include: Up to 4 DMA channels Provide memory-to-memory, memory-to-peripheral, peripheral-to-peripheral, and peripheral-to-memory transfer Round Robin arbitration scheme with four priority levels Support chain transfer Support 8/16/32-bit data width transfer 2.6 I2C The I2C is a two-wire bidirectional serial bus. The I2C bus interface controller allows the host processor to serve as a master or slave residing on the I2C bus. Data are transmitted to and received from the I2C bus via a buffered interface. The features include: Support Master and Slave modes Programable standard and fast modes Support 7-bit, 10-bit and general call addressing modes Built in Glitch de-bounce circuits Programmable address in the slave mode Slave mode general call address detection 2.7 UART The features include: Programmable baud rates up to 115.2 Kbps Configurable Start, Stop, and Parity bits. Support DMA for large data transfer Fully programmable serial interface: - - - 5-, 6-, 7-, or 8-bit characters Even, odd, and no parity detection 1-, 1.5-, or 2-stop bit generation Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) *9 EM7A8620 Voice Over IP 2.8 I2S/SPI Controller The IS/SPI controller are friendly to connected external audio codec device. The IS interface transfers digitized audio between the system memory and an external IS Codec which is controlled by SPI interface. Support I2S or SPI functions Support Master mode or Slave mode Programmable frame/sync polarity, serial bit clock polarity and frequency. Programmable MSB or LSB first Programmable zero bits padding and right or left justification in I2S Mode Support DMA for large data transfer 2.9 PCM Controller The PCM controller provides PCM BUS for PCM data transferring between SLIC/DAA. The PCM controller features include: Support Master and Slave mode. Programmable serial bit clock frequency. Programmable frame sync length. Support DMA for large data transfer 2.10 LCD Dot Matrix Controller The Dot Matrix controller provides an asynchronous MPU command interface.The features include: Uniform LCD Dot Matrix Interface Programmable nibble mode or byte mode data/address bus 2.11 Timer It provides 3 independent sets of timers. The features include: Three independent 32-bit timer Internal clock source Support Interrupts when overflow and time-up Support decrementing mode 10 * Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) EM7A8620 Voice Over IP 2.12 Watch Dog Timer (WDT) The WDT generates one or a combination of the following signals: reset, interrupt or external interrupt. The features include: Support System Reset, Interrupt and/or External Interrupt when timeout 32-bit down counter Variable time-out period of reset Access protection Watchdog reset is asserted, which resets the system except the PMU and RTC. 2.13 Interrupt Controller The Interrupt Controller provides both FIQ and IRQ modes to the CPU. The features include: Support fast interrupt (FIQ) and standard interrupt (IRQ) Interrupts can be routed to either IRQ or FIQ Programmable edge or level trigger interrupt source with positive and negative directions Support de-bounce circuit for interrupt input sources Programmable enable or disable any interrupt source 2.14 General Purpose Input / Output 32 GPIOs are used to input / output data from system and device. The features include: Support configurable as interrupt function Programmable edge or level trigger in interrupt mode Each port can be pulled high or pulled low Programmable Input/Output function 2.15 Real Time Clock The RTC provides a basic alarm function or long time-based counter. The RTC is set to be 1Hz output and employed as a system timekeeper. The features include: Support sleep mode Support second, minute, hour and day counters Alarm Once-per-second, once-per-minute, once-per-hour, and once-per-day interrupts Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) * 11 EM7A8620 Voice Over IP 2.16 Power Management Most of the device's clock can be enabled or disabled by using the system configuration registers. The clock to any unit that is not being used is turned off to minimize the power consumption. The PMU provides a method to change the PLL frequency and various power modes. 2.17 Audio CODEC The Audio CODEC has the following features. 90-dB SNR sigma-delta DAC 92-dB SNR sigma-delta ADC 8K ~ 96KHz sampling rate Analog volume control with mute Stereo line inputs/outputs ADC multiplexed input for stereo-line inputs and microphone 12 * Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) EM7A8620 Voice Over IP 3. DC Characteristics 3.1 Absolute Maximum Ratings Symbol VCC VIN18 VIN3 VIN3 TSTG Core power supply Input voltage of 1.8v I/O Input voltage of 3.3V I/O Input voltage of 3.3V I/O with 5V tolerance Storage temperature Parameter Rating -0.3 to 3.6 -0.3 to 2.1 -0.3 to 3.63 -0.3 to 5.5 -40 to 150 Unit V V V V 3.2 Recommended Operating Conditions Symbol VCC18 VCC33 VCC18A VCC18I VIN3 Tj Ta ESD Core power supply Power supply of 3.3V I/O Power supply of 1.8V I/O Power supply of 1.8V I/O Input voltage of 3.3V I/O with 5V tolerance Commercial junction operating temperature Commercial ambient operating temperature HBM model ESD MM model ESD CDM model ESD Parameter Min. 1.65 3.0 1.65 1.65 0 0 0 1 Typ. 1.8 3.3 1.8 1.8 3.3 25 Max. 1.95 3.6 1.95 1.95 5.25 115 70 2000 200 Unit V V V V V V V V 3.3 I/O Pad Capacitance Symbol CIN COUT CBID Parameter Input capacitance Output capacitance Bi-directional capacitance Condition Min. Typ. 3.2 3.2 3.2 Max. Unit pF pF pF 3.4 DC Characteristics for 3.3V Operation Recommended operating conditions (VCC = 3.0V to 3.6V) Symbol VIL VIh Vt Descriptions Input low voltage Input high voltage Switching threshold Condition LVTTL LVTTL LVTTL 2.0 1.5 Min. Typ. Max. 0.8 Unit V V V * 13 Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) EM7A8620 Voice Over IP VtVt+ VOL VOH RPU RPD Schmitt trigger negative going LVTTL threshold voltage Schmitt trigger positive going LVTTL threshold voltage Output low voltage Output high voltage Input pull-up resistance Input pull-down resistance Input leakage current Input leakage current pull-up resistance Input leakage current pull-down resistance with with IOL = 2 ~ 16 mA IOL = -2 ~ -16 mA Vin = 0 Vin = 3.3V Vin = 3.3V or 0 Vin = 0 Vin = 3.3V 0.8 1.1 1.6 2.0 0.4 V V V V K K uA uA uA uA 2.4 40 40 -10 -15 15 -10 75 75 1 -45 45 1 190 190 10 -85 85 10 Iin IOZ Tri-state output leakage current 3.5 DC Characteristics for 1.8V Operation Recommended operating conditions (VCC = 1.65V to 1.95V) Symbol VIL VIh Vt VtVt+ VOL VOH RPU RPD Iin IOZ Descriptions Input low voltage Input high voltage Switching threshold Condition CMOS CMOS CMOS 0.59 1.05 0.85 0.71 0.98 1.14 0.4 1.22 40 40 -10 -10 75 75 1 1 190 190 10 10 Min. Typ. Max. 0.69 Unit V V V V V V V K K uA uA Schmitt trigger negative going CMOS threshold voltage Schmitt trigger positive going LVTTL threshold voltage Output low voltage Output high voltage Input pull-up resistance Input pull-down resistance Input leakage current Tri-state output leakage current IOL = 2 ~ 16 mA IOL = -2 ~ -16 mA PU = high PD = low PU = high PD = low Vin = 1.8V or 0 14 * Product Specification (V1.0) 3.8.2006 (This specification is subject to change without further notice) |
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